Etching process and device for cleaning semiconductor components, in particular power diodes

ABSTRACT

A plasma etching process for cleaning laterally exposed p-n junctions of semiconductor elements, in particular power diodes after soldering together the semiconductor chip in question and connection elements is proposed, wherein the etching gases employed are fluorine compounds. Since the process according to the present invention does not involve doping dependence and crystal orientation dependence, it produces essentially vertically oriented chip-edges after etching and as a result a lower failure rate compared to the known wet-etching process. Since numerous rinsing processes can also be dispensed with, the plasma etching process is more suitable for mass production.

FIELD OF THE INVENTION

The present invention relates to an etching process for cleaninglaterally exposed p-n junctions of semiconductor elements, especiallypower diodes, after the semiconductor chip in question has been providedwith connection elements, for example by soldering them together, and toan apparatus for carrying out the process.

BACKGROUND INFORMATION

The fabrication of, for example, power diodes conventionally involves,after the cold base, the diode chip and the top wire have been solderedtogether, a cleaning operation, by silicon removal, of the p-n junctionsof the diode chip, which up to this point are still laterally exposed,by means of a wet-chemical alkaline etching process, e.g., by means ofaqueous KOH, in order to develop the blocking ability of the p-njunctions. This known process has the drawback that the lateral siliconremoval takes place as a function of doping and crystal orientation, sothat the etching contours produced differ greatly in the various dopingregions in how pronounced they are. Moreover, capillary effects mayarise as a function of the shape of the connection elements.Furthermore, the etching solution is prone to external contamination,and there is a concentration, temperature and agitation dependence and adependence on electrochemical potential differences specific to theetching system. In addition, this wet-chemical etching process is verycomplicated, owing to the numerous rinsing processes required. Thesedrawbacks as a whole, particularly in mass production, again and againlead to considerable losses in yield, whose causes are very difficult tofind, owing to the large number of mechanisms involved.

While plasma etching processes are known in semiconductor technology,they are employed almost exclusively in the production of wafers.

It is an object of the present invention to provide an etching processof the type mentioned at the outset and an apparatus for carrying itout, by means of which process improved etching contours can be achievedindependent of the doping profile of the laterally exposed semiconductorchips.

SUMMARY OF THE INVENTION

The plasma etching process according to the present invention, for thepurpose of cleaning the laterally exposed p-n junctions of semiconductorelements, has the advantage, compared with the wet-chemical alkalineetching process, that the achievable etching contours on the individualcomponent are far superior to those in the case of wet etching, the chipedge formed, in particular, running almost vertically in the case ofplasma etching.

This advantage of the plasma etching process according to the presentinvention makes it possible even to treat diodes having very shallow(i.e., situated close to the connection elements) p-n junctions whichare very inadequately dealt with in the course of wet etching. Typicaldepths in the process are 10-20 μm. The main reason for these advantagesis that the plasma etching process is largely independent of orientationand doping. Because the numerous rinsing processes are dispensed with,the plasma etching process is particularly suitable for mass production,and the yield can even be improved, compared with the wet--chemicaletching process, if process parameters are suitably chosen.

The etching gases employed include, for example, nitrogen fluorides,sulfur fluorides or carbon fluorides, especially CF₄, SF₆ or NF₃.

An advantageous implementation of the etching process according to thepresent invention includes in the etching gas, which has been ionized bythe injection of high-frequency electro-magnetic waves, especiallymicrowaves, being supplied in a plasma reaction vessel to thesemiconductor elements to be cleaned. In this arrangement, the etchinggas flows through the plasma reaction vessel at a pressure of preferably0.1-10 mbar.

So as to carry out the thermally activated etching operation as quicklyand optimally as possible, the semiconductor elements are expedientlyheated to a temperature below the melting point of the solder near themelting point. To enable as close and accurate a setting of saidtemperature as possible, a temperature control mechanism is found to beparticularly beneficial. For the purpose of heating, the semiconductorelements of the form indicated are placed with their cold bases onto aheating device, in particular a hotplate.

Even better results during the etching operation according to thepresent invention are achieved by the etching gas being admixed with anoxygen-containing gas, e.g., O₂ or N₂ O. The admixed gas makes itpossible to effect, in certain cases, a maximization of the etching ratewith simultaneous minimization of an etching gas-specific layerdeposition.

In the case of very highly blocking diodes, etching gas-specificcontaminants of the plasma etching process according to the presentinvention may cause the blocking-state voltage-current characteristicsof the diodes to be of insufficient quality and e.g., to showinstabilities. In order to achieve optimum results in this case, it isexpedient to carry out a wet-chemical or plasma-chemical aftertreatment.The wet-chemical after-treatment is preferably performed by means of adilute alkali (eg KOH) or deionized water. If a plasma-chemicalaftertreatment is preferred, this is carried out by means of an O₂ - orH₂ - or N₂ - containing plasma. Equally, tempering of the etched partsin an inert gas atmosphere (e.g., N₂ gas) is beneficial to the blockingability. This aftertreatment is applied for so short a time only,compared with the etching process according to the present invention,that the etching profile-determining process of plasma etching by meansof fluorine compounds is retained.

According to an advantageous arrangement for carrying out the etchingprocess according to the present invention, a plasma reaction vesselconnected to a pump and a system for generating a plasma from a gaseousfluorine compound as the etching gases are provided, a heating devicewhich accommodates the semiconductor elements to be treated and isprovided with through holes being arranged in the plasma reactionvessel. The system for generating the plasma is expediently disposedupstream of the plasma reaction vessel and has a feed line for thegaseous fluorine compound.

The heating device for heating the semiconductor elements expedientlycomprises at least one hotplate. Connected thereto there is atemperature controller.

BRIEF DESCRIPTION OF THE DRAWINGS

An illustrative embodiment of an apparatus for carrying out the etchingprocess according to the present invention is shown in the drawing andexplained in more detail in the following description.

FIG. 1 is a diagrammatic depiction of a plasma reaction vessel accordingto the present invention.

FIG. 2 shows a detail drawing of an edge zone of the semiconductor chipbefore and after etching according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The plasma etching apparatus depicted in FIG. 1 includes a plasmareaction vessel 10 which is fed, via a line 11, with plasma generated ina plasma generator 12. The plasma generator 12 is initially fed with agaseous fluorine compound as the starting material for the plasma. Thisis, for example, a nitrogen fluoride, sulfur fluoride or carbon fluoridesuch as nitrogen trifluoride (NF₃), sulfur hexafluoride (SF₆) or carbontetrafluoride (CF₄). Such an etching gas is further admixed with anoxygen-containing gas such as O₂ or N₂ O or the like, in order toeffect, in certain cases, a maximization of the etching rate while atthe same time minimizing an etching gas-specific layer deposition. Inother cases, this additional gas can also be omitted.

The plasma generator 12 generates high-frequency electromagnetic waves,such as microwaves, which, by injection, ionize the etching gas beingpassed through. The free radicals and the ions produced may enter intochemical and physical interactions with solids. These processes takeplace at a pressure of, typically, 1 mbar, a pressure between 0.1 and 10mbar being possible in individual cases. The throughput of the ionizedetching gas through the reaction vessel 10 is effected by means of apump P (not shown).

Because of the etching contour uniformity aimed for, care should betaken in the construction of the plasma generator 12 to precludetroublesome anisotropic physical interactions, e.g., impact processes.

Disposed in the reaction vessel 10 there is a hotplate 13 which isbrought to a desired temperature by means of a temperature controller14. The temperature is below the melting point of that component of amounted semiconductor element to be treated, which has the lowestmelting point. In general, this component will be the solder used. Thehotplate 13 has ducts 15 which run parallel to the flow of the etchinggas in order to improve flow. For the sake of simplification, only asingle hotplate 13 is shown, but it is of course possible for a largernumber of hotplates to be provided in the reaction vessel 10.

Onto the hotplate 13, the mounted or ready-soldered semiconductorelements are now placed. In the case of the illustrative embodimentaccording to the present invention shown, this involves a power diode 16which, for the sake of illustration, is shown enlarged. In the practicalapplication, a multiplicity of such semiconductor elements or powerdiodes is arranged on the hotplate 13 or the hotplates, and those arejointly subjected to the plasma etching process according to the presentinvention.

The power diode 16 shown includes a cold base 17, a diode chip 18 and atop wire connection 19. These three elements are joined together viasolder layers 20, 21. In this arrangement, the power diode 16 rests onthe hotplate 13 by its cold base 17, in order to ensure rapid andreliable heating.

As shown in FIG. 2 in enlarged detail, the diode chip 18 includes threelayers, for example, a boron-(p⁺ -) doped layer 22, a phosphorus- (n-)doped layer 23 and a phosphorus- (n⁺ -) doped layer 24. To enable thediode chip 18 to be soldered on, the latter is provided, at its shallowsides, with a nickel layer 25. After the power diode 16 has beensoldered together, cleaning of the until then still laterally exposedp-n junctions by means of removal of silicon is required, in order todevelop the blocking ability of the p-n junctions. The cleaning orsilicon removal is effected by means of the plasma etching processaccording to the present invention. On the grounds of isotropy andhomogeneity, the only matter of interest in the application of thisplasma etching process is the chemical interaction of the free radicalsand ions contained in the plasma with the diode chip 18. Knowncommercial plasma etching installations which operate according to thedownstream principle, are able to preclude any troublesome physicalinteractions, the prerequisite being the use of microwave excitation bythe plasma generator 12. This results in the formation of long-livedetching free radicals having lifetimes of up to 1 second in terms oforder of magnitude.

An important factor during etching is the temperature, since the etchingoperation is a thermally activated process. Heating of the diode chip 18is effected--as has already been described--via the hotplate 13 and thecold base 17, arranged thereon, of the power diode 16. The gas flowrates of the etching gas should be chosen in accordance with the loadinglevel of power diodes 16 or other semiconductor elements.

The plasma etching process according to the present invention allows anetching contour to be achieved as depicted by a dashed line 26. The chipedge after plasma etching runs almost vertically, whereas the wetetching profile emerging in the case of the known wet etching showscharacteristic traces of orientation dependence and doping dependence.The wet etching profile is represented by a dot-and-dash line 27.

In the case of very highly blocking diodes, etching gas-specificcontaminants of the plasma etching process described may result in theblocking-state voltage-current characteristics of the diodes being ofinsufficient quality and e.g., showing instabilities. To prevent this, awet-chemical aftertreatment can be carried out in dilute alkali (e.g.,KOH) or deionized water. In comparison with the conventional wet-etchingprocess, this process is applied only for so short a time, that theetching profile-determining process of plasma etching remains, i.e.,that the etching profile 26 is retained.

Alternatively, a plasma-chemical aftertreatment in an O₂ -, N₂ - or H₂-containing plasma can be carried out. Although the etching processaccording to the invention has been described for a specific type ofsemiconductor diodes comprising a characteristic semiconductor chip andspecial connection elements, the invention is of course not limited tothis specific embodiment.

What is claimed is:
 1. An etching method for a semiconductor element,the semiconductor element including a semiconductor chip and a laterallyexposed p-n junction the semiconductor chip being joined to each of acold base element and to a connection element via a respective solderlayer, comprising the steps of:receiving plasma via an inlet of a plasmareaction vessel: removing the plasma via an outlet of the plasmareaction vessel, the outlet being positioned opposite to the inlet, theinlet and the outlet defining a flow direction of the plasma; providinga plate-like heating device arranged substantially transverse to theflow direction of the plasma, the heating device arranging thesemiconductor element on the cold base element and having at least onethrough-hole arranged substantially in the flow direction of the plasmaso that the plasma flows laterally past the exposed p-n function; andheating the semiconductor element, using the heating device coupled to atemperature controller, to regulate a temperature of the semiconductorelement to be in a range between room temperature and a melting point ofthe respective solder layer.
 2. The etching method according to claim 1,wherein the temperature is in the region of the melting point of thesolder.
 3. The etching method according to claim 1, further comprisingthe step of admixing the at least one etching gas with anoxygen-containing gas.
 4. The etching method according to claim 3,wherein the oxygen-containing gas includes one of O₂ and N₂ O.
 5. Theetching method according to claim 1, further comprising the step ofapplying an aftertreatment, the aftertreatment including one of athermal aftertreatment, a wet-chemical aftertreatment and aplasma-chemical aftertreatment.
 6. The etching method according to claim5, wherein the wet-chemical aftertreatment is accomplished via one of adilute alkali and a deionized water.
 7. The etching method according toclaim 5, wherein the plasma-chemical aftertreatment is accomplished viaone of an O₂ -, an H₂ -, and a N₂ - containing plasma.
 8. The etchingmethod according to claim 1, wherein the step of applying the at leastone etching gas further includes the steps of:ionizing the at least oneetching gas via an injection of high-frequency electromagnetic waves;and supplying the ionized at least one etching gas in a plasma reactionvessel.
 9. The etching method according to claim 8, wherein theelectromagnetic waves include microwaves.
 10. The etching methodaccording to claim 8, wherein the at least one etching gas flows throughthe plasma reaction vessel.
 11. An apparatus for etching a semiconductorelement that includes a semiconductor chip and a laterally exposed p-njunction, the semiconductor chip being Joined to each of a cold base andto a connection element via a respective solder layer, comprising:aplasma reaction vessel having an inlet for accepting plasma and anoutlet positioned opposite to the inlet for removing the plasma, theinlet and the outlet defining a flow direction of the plasma; aplate-like heating device disposed in the plasma reaction vessel forheating the semiconductor element and arranged substantially in atraverse direction to the flow direction of the plasma, the heatingdevice arranging the semiconductor element on the cold base and havingat least one through-hole extending in the flow direction of the plasmaso that the plasma flows laterally past the exposed D-n junction; and atemperature controller coupled to the heating device for regulating atemperature of the semiconductor element to be between room temperatureand a melting point of the respective solder layer.
 12. The apparatusaccording to claim 11, wherein the plasma generating system includes afeed line for the gaseous fluorine compound and the plasma generatingsystem is disposed upstream of the plasma reaction vessel.
 13. Theapparatus according to claim 11, wherein the plasma generating systemincludes a microwave generator.
 14. An etching method for cleaning alaterally exposed p-n junction of a semiconductor element after thesemiconductor element has been soldered to a connection element,comprising the steps of:providing a heating device including at leastone through-hole; heating the semiconductor element, using the heatingdevice, to a temperature in a range between room temperature and amelting point of a solder used to solder the semiconductor element tothe connection element; and applying at least one etching gas to thesemiconductor element, the at least one etching gas including a fluorinecompound.
 15. The etching method according to claim 14, wherein the atleast one through-hole of the heating device extends parallel to a flowdirection of the at least one etching gas for allowing the at least oneetching gas to circulate through the at least one through-hole.
 16. Anapparatus for applying an etching technique for cleaning a laterallyexposed p-n junction of a semiconductor element after the semiconductorelement has been soldered to a connection element, comprising:a plasmareaction vessel having first through-holes disposed therethrough; a pumpsystem coupled to the plasma reaction vessel; a plasma generating systemcoupled to the plasma reaction vessel for generating at least oneetching gas from a gaseous fluorine compound; and a heating devicedisposed in the plasma reaction vessel for heating the semiconductorelement, the heating device having at least one second through-hole. 17.The apparatus according to claim 16, wherein the at least one secondthrough-hole of the heating device extends parallel to a flow directionof the at least one etching gas for allowing the at least one etchinggas to circulate through the at least one second through-hole.
 18. Themethod according to claim 1, wherein the semiconductor element includesa power diode.
 19. The apparatus according to claim 11, wherein thesemiconductor element includes a power diode.